1. Field of the Invention
This invention relates to an improved in-between phase clamping circuit compatible with a multi-phase, major-minor clocking scheme to reduce the effects of positive noise.
2. Prior Art
Integrated circuit field effect transistor (FET) logic circuits, which are strobed by a four-phase, major-minor clocking scheme can be arranged to form six basic logic gates. One logic gate, commonly designated as a type 2 logic gate (which precharges when multi-phase clock-signal .phi..sub.1 is true and discharges or evaluates when multi-phase clock signal .phi..sub.2 is true), and a second logic gate, commonly designated as a type 4 logic gate (which precharges during .phi..sub.3 and evaluates during .phi..sub.4), are referred to as major logic gates by those skilled in the art, inasmuch as each gate evaluates during major clock phases .phi..sub.2 and .phi..sub.4, respectively. For a more detailed description of major logic gate types 2 and 4, reference may be made to U.S. Pat. No. 3,601,627 issued Aug. 24, 1971, and to U.S. application Ser. No. 659,057 filed Feb. 18, 1976.
Positive noise is a well-known problem associated with the utilization of the aforementioned type 2 and 4 major logic gates. That is, the output signal of these major gates is susceptible to the effects of positive noise during minor clock phases 1 and 3 and during in-between clock phases, when the major gates are holding or storing information. The in-between clock phases correspond to the intervals of time between the occurrence of first and second major clock phases. Such undesirable noise typically results as a consequence of capacitive coupling between type 2 and 4 logic gates with other logic gates and during the negative transition of the multi-phase clock signal generator. Positive noise at the output terminal of a logic gate may result in the deterioration of a negative output signal to a level where relatively negative and positive output signals become indistinguishable from one another.
Reference can be made to U.S. Pat. No. 3,567,968 issued Mar. 2, 1971 and U.S. Pat. No. 3,774,053 issued Nov. 20, 1973, for examples of prior art circuits which eliminate the effects of noise in multi-phase field effect transistor logic circuits. However, no circuits are known which reduce the effects of positive noise during both the minor clock phases and the in-between clock phase of a four phase major-minor scheme.